The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, phase-change memory operates under the passage of an electric current through a heating element for quickly heating and quenching the phase-change material into amorphous or crystalline states, and it is generally desired to fabricate as small as possible the heating element. A compact heating element, such as a via made by titanium nitride (TiN) in physical contact with the phase-change material in some embodiments, helps to reduce phase-change memory's form factor due to its smaller size, and also increases phase-change memory's speed due to its higher heating efficiency. However, as semiconductor technology progresses to smaller geometries, not limited to phase-change memory, the traditional photoresist approach for via patterning is restrained by resolution and ingredients of photoresist component, which may suffer from photoresist scum and poor critical dimension uniformity (CDU) issues. Therefore, although existing approaches in via formation have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.